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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

storing link rates in ATX PLL

Hi I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, In this it uses fpll and stores calibrated link rates for different speeds, can we implem...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Rajesh,


As I understand it, you have some inquiries related to storing link rates in ATX PLL. Please correct me if I am wrong, I believe you are referring to dynamic reconfiguring the ATX PLL to different data rates. If yes, for your information, ATX PLL supports multi-profiles reconfiguration. In other words, you can preconfigure a number of frequency profiles and by writing to a few registers, it will auto reconfigure for you. You may refer to section "Multiple Reconfiguration Profiles" and "6.5 Embedded Reconfiguration Streamer" in the A10 Transceiver PHY User Guide for further details.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin