TChin5
New Contributor
7 years agoStill cannot assign LVDS signal to MAX-V device
I try your suggestion. I have a single-ended signal call OUT_P and assigned it as LVDS_E_3R, the pin planner created the corresponding diff signal call OUT_P(P).
When I compile it, Quartus returns a pop-up problem report window.
The short version of the Preview of the report :
Problem Details
Error:
Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing
Stack Trace: ....................................
................................
Executable: quartus_fit
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 17.1.0
Build: 590
Edition: Lite Edition