Steps to constrain a design

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I think for source synchronous, there are cases where you can do a multicycle -setup 2, but you don't want to do a multicycle -hold 1, as that will mean you're running at a lower rater. (I always make sure the clock is shifted into the center of the data window, in which case you don't need to add any multicycles.) I haven't ever added a hold multicycle to a source-sync interface, but don't know what specific case you're talking about.

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With delay determined by fitter you cannot guarantee centre aligned clock across all paths in a large design so a hold multicycle is necessary in order for multicycle to be meaningful and helpful. In all my designs of multicycle I do relax both setup and hold otherwise there will will serious violations. There is no place for lower rate running concept here; we are just telling the tool which edges to check.