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Altera_Forum
Honored Contributor
Honored ContributorSteps to constrain a design
Hello, I'm trying to understand timing constraints and I have a really hard time trying to figure out how this works. The first thing is the representation of setup and hold times. In my e...
Altera_ForumHonored Contributor
Honored ContributorI think for source synchronous, there are cases where you can do a multicycle -setup 2, but you don't want to do a multicycle -hold 1, as that will mean you're running at a lower rater. (I always make sure the clock is shifted into the center of the data window, in which case you don't need to add any multicycles.) I haven't ever added a hold multicycle to a source-sync interface, but don't know what specific case you're talking about.
