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Altera_Forum
Honored Contributor
Honored ContributorSteps to constrain a design
Hello, I'm trying to understand timing constraints and I have a really hard time trying to figure out how this works. The first thing is the representation of setup and hold times. In my e...
Altera_ForumHonored Contributor
Honored ContributorMy reply was about source synchronous clock path and for this case adding a multicycle of 2 to a path must be associated with hold multicycle of 1 because only then the tool can check the relevant edges. For cases such as phase shifted launch/latch clocks then the user will need to see if they have to design for an extra setup multicycle and whether to add to hold multicycle or not.
