std_logic_vector vs array

gmpstr,

Very interesting! I'm glad I checked this out as it leads into something I'm trying now.

I looked this up in my copy of "The Designer's Guide To VHDL" 2nd Edition by Peter Ashenden. Now I thought I was taught that VHDL cannot handle multidimentional arrays, I remembered wrong!

In the book on page 88 he goes into multidimensional arrays, for some reason he likes using the lesser used standard types in his examples but here's his example (he also assumes we're smart enough to put in the proper VHDL file format);

*skip*

TYPE point IS ARRAY (1 TO 3) OF real;

TYPE matrix IS ARRAY (1 TO 3, 1 TO 3) OF real;

*skip*

VARIABLE p,q : point;

VARIABLE transform : matrix;

*skip*

For i IN 1 TO 3 LOOP

q(i) := 0.0;

For j IN 1 TO 3 LOOP

q(i) := q(i) + transform(i,j) * p(j);

END LOOP;

END LOOP;

Now for this he states that this is a design to handle a three dimensional array where 'p' and 'q' are the point variables for the matrix transform.

I don't know if this will help but its what I've got.

I've been doing some more research and try this;

Don't use STD_LOGIC_VECTOR, it is an unconstrained array. Declare your own array of STD_LOGIC (not _VECTOR) creating your own constrained array. Use STD_LOGIC as the example above uses REAL.

Give it a shot.