std_logic_vector vs array

Thanks for the reply.

What I realy need is to be able to have an array in the port entity.

This is what I'd like:

entity x is

generic(

constant_1 : integer := 50);

port (

in_port : in array(0 to constant_1 -1) of std_logic_vector(7 downto 0));

end x;

I know that "in_port : in array(0 to constant_1 -1) of std_logic_vector(7 downto 0) is not legal in VHDL, but it shows what I'd like to do. This needs to be done because x is called at an upper level file twice with different values of constant_1 passed in. I want to size in_port differently based on the instantiation on the upper level file while using the same code.

Currently, I have this:

entity x is

port (

in_port : in in_port_array_type);

end x;

Where in_port_array_type is defined in a package file. But this does not allow sizing in_port_array_type differently in different instantiations of x.

I suppose I could make in_port a std_logic_vector with a range of...

((constant_1*8) -1 downto 0)

and then map it into an array type defined in x, rather than a package file.

So, if there is any way to have an array in the port, that would be the best. If someone knows how or if this can be done, please let me know. If I have to just make it a large std_logic_vector and map that vector to an array defined in the code, then thats the way I'll go.