State of Unused I/O pins and design of isolation filter for Cyclone IV FPGA

The suggested capacitors is for the whole power plane, not per pin. It doesn't seem to be a lot, are you sure you put the right current requirements in the sheet?

As for the plls supplies they are also use for other things, such as the configuration and JTAG internal logic. But I guess that it won't be that critical. I think you can avoid using ferrite, but you'll never get a guarantee that such a setting is safe. Besides, later in the project you could decide that you need a pll for an extra clock frequency that you didn't think about. Ferrites are rather small, so at least having the 0603 or 0402 footprint just in case you need the ferrite later would be safer IMHO.