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Altera_Forum
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13 years ago

State of Unused I/O pins and design of isolation filter for Cyclone IV FPGA

Hello there, Reference: Cyclone 4 EP4CE10 FPGA I m developing a prototype board with minimum peripheral say 4 slide switches, and 4 LEDs, with a 40pin GPIO, with program persistance throug...
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Altera_Forum
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12 years ago

Dear Daixiwen,

How to ensure the enough decoupling is present on each FPGA supply ? What is the suggested values of decoupling capacitors on each VCCINT & VCCD_PLL (@1.2V)supplies & Similarly on each VCCA & VCCA_PLL(@2.5v).

I am not using any PLLs inside FPGA. I am using maximum FPGA I/O signal frequency is @150MHz.

Please guide me how to calculate decoupling on these FPGA power pins. I am using cyclone - IV E FPGA.

Regards,

Thulasi