State of Unused I/O pins and design of isolation filter for Cyclone IV FPGA

For your GPIO pins you can leave them floating if you have pull-ups or pull-downs. Without them the pin voltage could oscillate and increase the chip consumption. You can either put some pull-us/downs on the board or use the assignment editor or pin planner to enable the internal pull-ups in the FPGA on those pins.

As for the filter between two supplies of the same value, we usually put a ferrite. If you have enough decoupling on both FPGA supplies it should be enough. As an example you can download one of the FPGA development kit support files and have a look at the schematics.