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Altera_Forum's avatar
Altera_Forum
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17 years ago

state machine design little help

I completed a cyclic code in verilog and is working (finally) as expected. But I had to switch to MAXII since code become quite large, especially when I complete a case statement with all constants required :)

Now I think to re-design a little bit: I need 1 shot executable set of events, triggered externally (say START pin). After events completed, it would be nice system to re-enter automatically in IDLE state so I can trigger more. Of course, after first trigger, next will be ignored until complete.

If glue-logic, I'd use a S-R latch but as far as I read it's not a good idea. So I begun something in verilog and I need little help 

always @(posedge start)
begin
    go = 1;
end
always @(posedge ck)
begin
        if(go && ~reset)
        begin
            cnt = cnt+1;
            if(cnt==20) event=1;
            if(cnt==30) 
            begin 
                event=0;
                reset=1; // one time
            end    
        end
end

My code is executed only once because I cannot reset 'go' variable after event completed (sync on ck). Any idea appreciated.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    reg        start_r;
reg        cnt;
reg             go;
reg             reset;
always @(posedge ck)
begin
                        start_r <= {start_r,start}; // latch start signal
                        reset   <= 1'b0;    // default to zero
        if(go) begin
                        cnt     <= cnt+5'd1;// increment count
            if(cnt==20) event   <= 1'b1;    // set event flag
            if(cnt==30) begin
                        event   <= 1'b0;    // clear event flag
                        go      <= 1'b0;    // clear go flag
                        reset   <= 1'b1;    // one clock wide
            end
        end else begin
                        go  <= ~start_r & start_r; // go on rising start endge
                        cnt <= 5'd0;
        end
end

    Jake