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Altera_Forum
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16 years ago

state machine design little help

I completed a cyclic code in verilog and is working (finally) as expected. But I had to switch to MAXII since code become quite large, especially when I complete a case statement with all constants r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

reg        start_r;
reg        cnt;
reg             go;
reg             reset;
always @(posedge ck)
begin
                        start_r <= {start_r,start}; // latch start signal
                        reset   <= 1'b0;    // default to zero
        if(go) begin
                        cnt     <= cnt+5'd1;// increment count
            if(cnt==20) event   <= 1'b1;    // set event flag
            if(cnt==30) begin
                        event   <= 1'b0;    // clear event flag
                        go      <= 1'b0;    // clear go flag
                        reset   <= 1'b1;    // one clock wide
            end
        end else begin
                        go  <= ~start_r & start_r; // go on rising start endge
                        cnt <= 5'd0;
        end
end

Jake