state machine design little help

reg        start_r;
reg        cnt;
reg             go;
reg             reset;
always @(posedge ck)
begin
                        start_r <= {start_r,start}; // latch start signal
                        reset   <= 1'b0;    // default to zero
        if(go) begin
                        cnt     <= cnt+5'd1;// increment count
            if(cnt==20) event   <= 1'b1;    // set event flag
            if(cnt==30) begin
                        event   <= 1'b0;    // clear event flag
                        go      <= 1'b0;    // clear go flag
                        reset   <= 1'b1;    // one clock wide
            end
        end else begin
                        go  <= ~start_r & start_r; // go on rising start endge
                        cnt <= 5'd0;
        end
end