State Machine- State doesn't set logic as expected

Do not use buffer(obsolete).Your state transition is tied up to elsif...

If you just want to serialise 24 bits into time muxed 6 bits then there might be easier ways of doing what you want e.g.

signal count: integer range 0 to 3;
 
process(reset,clk)
begin
if reset = '1' then
   count <= 0;
   input_en <= '0';
   BusOut <= (others => '0');
 elsif rising_edge(clk) then
 
   count <= count + 1;
 
   case count is
      when 0 => BusOut <= BusIn(17 downto 12); input_en <= '1';
      when 1 => BusOut<= BusIn(23 downto 18); input_en <= '0';
      when 2 => BusOut <= BusIn(5 downto 0); input_en <= '0';
      when 3 => BusOut <= BusIn(11 downto 6); input_en <= '0';
   end case;
end process;

the input_en pulse is to control the input rate(= input clk/4). It needs some care to synchronise the data request to the front module. I have assumed the request is raised at count 0, becomes high at count 1 and data is available soon at count 2. Such design is called pull data flow(not push)