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Honored Contributor
Honored ContributorSTA and Timequest relation
Hello everyone, i am fresher to VLSI fiels. I am doing Verilog/VHDL coding for last 10 months. I come across these back end terms of Constraining, Timing and fitting the design on FPGA. I read about ...
Altera_ForumHonored Contributor
Honored ContributorA good place to start is with the timequest timing analyzer quick start tutorial (http://www.altera.com/literature/ug/ug_tq_tutorial.pdf).
Constraints help Quartus to fit your design so that it meets your timing requirements. Quartus will work as hard as necessary to meet the timing constraints you've specified. Only when it can't meet them will it report a timing violation. This is similar to performing STA once your design is complete only Quartus has a set of rules to determine if it's met timing, rather than leaving you to analyse the results of STA. Happy New Year, Alex
