Hi everyone, I started doing SSN analysis on my preliminary designs and I found that I had problems with my standard PCI signals (3.0V) creating SSN on other 3.0V I/Os and vice versa. I tried a lot of different solutions (fitter placing the pins, etc.) but the one that seemed to work best was to set a lot of pins as reserve to ground. Now it seems to work fine, every I/O on my 3.0V banks now pass the SSN analysis however I get lots of errors for my reserved pins driven to ground. Why is that? How can there be SSN on pins that drive ground directly? Is this a real problem or can I explain it away? Best regards

what exactly do you mean by getting errors on the reserved pins?

I mean SSN errors. i.e. more than 80 or 90% of noise on the reserved ground pins (I set them using pin planner)

--- Quote Start --- I mean SSN errors. i.e. more than 80 or 90% of noise on the reserved ground pins (I set them using pin planner) --- Quote End --- Reserving pins as ground in the pin planner does nothing but tell the pin planner you have connected those pins to ground. If you haven't actually done that on the PCB, then you will not gain any advantage. Cheers, Dave

Hi, The PCB isn't done yet, I'm trying to perform pre-layout SSN optimisation as suggested in " the "Design Guidelines for Arria II Device" application note

Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN. Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors. If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.

SSN and reserve pins as ground | Altera Community

15 Replies

Altera_Forum
Honored Contributor
14 years ago
Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN.

Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors.

If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.
Altera_Forum
Honored Contributor
14 years ago
Hi,

The PCB isn't done yet, I'm trying to perform pre-layout SSN optimisation as suggested in " the "Design Guidelines for Arria II Device" application note
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
I mean SSN errors. i.e. more than 80 or 90% of noise on the reserved ground pins (I set them using pin planner)
--- Quote End ---

Reserving pins as ground in the pin planner does nothing but tell the pin planner you have connected those pins to ground. If you haven't actually done that on the PCB, then you will not gain any advantage.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
I mean SSN errors. i.e. more than 80 or 90% of noise on the reserved ground pins (I set them using pin planner)
Altera_Forum
Honored Contributor
14 years ago
what exactly do you mean by getting errors on the reserved pins?

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SSN and reserve pins as ground

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