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Altera_Forum
Honored Contributor
Honored ContributorSRFF VHDL implementation
Hello. I'm trying to build SR flip-flop with VHDL. Here is the code: entity first is port(s,r:in bit;q,nq:buffer bit); end first; architecture first_arc of first is begin ...
Altera_ForumHonored Contributor
Honored ContributorThis code is no safe in fpgas at all.
1) combinatorial feedback not recommended. 2) latches not recommended in rtl 3) buffer is not used except in Uni lectures. 4) if you want register, just use single clked statement.
