SRAM verification error afte change LVDS pins

I use a SGDMA to stream a Frambuffer from SRAM to Display via LVDS

when e put a second LVDS Display to the same pins, i got a SRAM verification error during softwaretransfer from NIOS IDE via jtag.

I don't see the relationship between FPGA-LVDS (3R) pins, and the read-write process of SRAM.

Do you know, how i kann find the cause of this problem?