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Altera_Forum's avatar
Altera_Forum
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16 years ago

SRAM controller in SOPC buil

Hi,

Actually my project contains ISSI SRAM 512x16 bit. On my board there are two of these cascaded. While testing, I used the memtest code given in NIOS IDE. My hardware image contained NIOS processor, JTAG, onchip memory, tristate bridge and IDT controller (which I found having similar timing as my ISSI SRAM). The test was successful. My main confusion arose, when I probed the IC with CRO. I found that even when I had downloaded only sof file, there were some periodic pattern on pins of IC. Is it that controller in SOPC gives some periodic signals out? As I had expected no signal on pins till there was no software run.

Regards,

Saransh

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    NIOS processor is set to boot from onchip memory. I wanted to confirm whether the controller of SRAM keeps on sending some set pattern on its pins, even when software code is not running?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Where is the NIOS processor set to boot from? How do you know it's not running "code". It may be random junk.

    Jake