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Altera_Forum
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14 years ago

SPI with variable datalength

Hello,

At this moment I am using the Avalon SPI core from Altera to interface to a ADC/DAC. I also want to use this to interface to a serial EEPROM but the data-length for the EEPROM I want to use is 29 bits instead of 16 bits when interfacing to the ADC/DAC. Has anybody modified the Avalon SPI core from Altera so that the number of data-bits can be specified during the execution of the program or is there a Avalon SPI core available which I can use.

Best regards,

Wamor

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    At this moment I am using the Avalon SPI core from Altera to interface to a ADC/DAC. I also want to use this to interface to a serial EEPROM but the data-length for the EEPROM I want to use is 29 bits instead of 16 bits when interfacing to the ADC/DAC. Has anybody modified the Avalon SPI core from Altera so that the number of data-bits can be specified during the execution of the program or is there a Avalon SPI core available which I can use.

    --- Quote End ---

    SPI controllers (on microcontrollers) generally only 'talk' in 8-bit transactions, and its up to your driver to assert chip-select for the number of 8-bit transactions your device really cares about. Even if your EEPROM has a 29-bits command code/format, there is a pretty good chance you can just talk to it using 32-bits. You'll just need to read the data sheet to determine when the EEPROM starts to ignore bits, i.e., is it the first or last 3-bits of the 32-bit transaction that get ignored.

    Alternatively, just write a controller to interface to the EEPROM.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    I agree with Dave.

    For example serial DAC/ADC usually synchronize data to a chip select signal or latch enable pulse, so that only last bits of the spi word are actually used; the others are simply shifted out and discarded. Same for spi rx: you discard the extra bits.

    You must evaluate if your spi slaves use protocols which allow this.

    Should they not, or if you want a simpler solution and you have enough spare fpga resources, you can even instantiate two spi cores with different word lengths. This may be convenient if one spi port is tx only, like in the typical case of a DAC.

    Cris