SPI with variable datalength

I agree with Dave.

For example serial DAC/ADC usually synchronize data to a chip select signal or latch enable pulse, so that only last bits of the spi word are actually used; the others are simply shifted out and discarded. Same for spi rx: you discard the extra bits.

You must evaluate if your spi slaves use protocols which allow this.

Should they not, or if you want a simpler solution and you have enough spare fpga resources, you can even instantiate two spi cores with different word lengths. This may be convenient if one spi port is tx only, like in the typical case of a DAC.

Cris