SPI ram and Nios on FPGA MAX10

Yes,

I would like a hardware module that allows NiosII to see the external SPI ram as regular RAM (obviously slower then a real RAM).

I resolved this problem: I wrote my hardware module (in VHDL) and I used a Avalon-MM Pipelined Bridge to export the Avalon-MM bus to this module (extern to NiosII).

This module manages on one hand the interfacing with NiosII (raises the waitrequest signal in order to stop the execution of the code until it has completed the operation with external RAM, asserts data for the read operations etc. etc.) and on the other hand manages the communication from/towards the external SPI ram according to the rules of the ram itself.

In the application code of NiosII (C code) I allocate in the address space provided by the Avalon-MM Pipelined Bridge the variables, the stack and all the rest of my application (apart from the exception code that I run in the internal ram for reasons of execution speed).

Regards,

Perryiavo.