SPI Interface

Yes,

that´s right. You have to conect the wishbone signals with the nios signals in the top sheet.

--- Quote Start ---

module MICRO_SD_TOP

( //NIOSII

input wire NIOS_CLK,

input wire SPI_CLK, //48MHz

input wire NIOS_CSn,

input wire NIOS_WRn,

input wire NIOS_RDn,

input wire [5:0] NIOS_ADDR,

input wire [3:0] NIOS_BE,

input wire [31:0] NIOS_DATAout,

output wire [31:0] NIOS_DATAin,

input wire RESET,

output wire NIOS_WAITREQn,

//SD_CARD

output wire SD_DATA_OUT,

input wire SD_DATA_IN,

output wire SD_CS,

output wire SD_CLK

);

wire [7:0] SD_DATA_O;

wire [7:0] SD_DATA_I;

wire [7:0] SD_ADDR_I;

assign NIOS_DATAin[7:0] = ( ~NIOS_CSn && ~NIOS_RDn && (NIOS_BE[3:0] == 4'b0001) ) ? SD_DATA_O[7:0] : 8'hzz;

assign NIOS_DATAin[15:8] = ( ~NIOS_CSn && ~NIOS_RDn && (NIOS_BE[3:0] == 4'b0010) ) ? SD_DATA_O[7:0] : 8'hzz;

assign NIOS_DATAin[23:16] = ( ~NIOS_CSn && ~NIOS_RDn && (NIOS_BE[3:0] == 4'b0100) ) ? SD_DATA_O[7:0] : 8'hzz;

assign NIOS_DATAin[31:24] = ( ~NIOS_CSn && ~NIOS_RDn && (NIOS_BE[3:0] == 4'b1000) ) ? SD_DATA_O[7:0] : 8'hzz;

assign SD_DATA_I[7:0] = ( ~NIOS_CSn && ~NIOS_WRn && (NIOS_BE[3:0] == 4'b0001) ) ? NIOS_DATAout[7:0] : 8'hzz;

assign SD_DATA_I[7:0] = ( ~NIOS_CSn && ~NIOS_WRn && (NIOS_BE[3:0] == 4'b0010) ) ? NIOS_DATAout[15:8] : 8'hzz;

assign SD_DATA_I[7:0] = ( ~NIOS_CSn && ~NIOS_WRn && (NIOS_BE[3:0] == 4'b0100) ) ? NIOS_DATAout[23:16] : 8'hzz;

assign SD_DATA_I[7:0] = ( ~NIOS_CSn && ~NIOS_WRn && (NIOS_BE[3:0] == 4'b1000) ) ? NIOS_DATAout[31:24] : 8'hzz;

assign SD_ADDR_I[7:2] = NIOS_ADDR[5:0];

assign SD_ADDR_I[1:0] = ( ~NIOS_CSn && (NIOS_BE[3:0] == 4'b0001) ) ? 2'b00 : 2'bzz;

assign SD_ADDR_I[1:0] = ( ~NIOS_CSn && (NIOS_BE[3:0] == 4'b0010) ) ? 2'b01 : 2'bzz;

assign SD_ADDR_I[1:0] = ( ~NIOS_CSn && (NIOS_BE[3:0] == 4'b0100) ) ? 2'b10 : 2'bzz;

assign SD_ADDR_I[1:0] = ( ~NIOS_CSn && (NIOS_BE[3:0] == 4'b1000) ) ? 2'b11 : 2'bzz;

spiMaster SD_CNTRL_inst

(

.clk_i(NIOS_CLK),

.rst_i(RESET),

.address_i(SD_ADDR_I),

.data_i(SD_DATA_I),

.data_o(SD_DATA_O),

.strobe_i(~NIOS_WRn | ~NIOS_RDn),

.we_i(~NIOS_WRn & NIOS_RDn),

.ack_o(NIOS_WAITREQn),

// SPI logic clock

.spiSysClk(SPI_CLK),

//SPI bus

.spiClkOut(SD_CLK),

.spiDataIn(SD_DATA_IN),

.spiDataOut(SD_DATA_OUT),

.spiCS_n(SD_CS)

);

--- Quote End ---