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Altera_Forum
Honored Contributor
Honored ContributorSpeed grades and internal timings
Hi,
Not so much a problem that I´m having just more something I would like to understand better. I am currently using a Stratix II GX I-Grade -4 FPGA for a project. I am using Modelsim to carry out timing simulations on my design and am wondering how the .vho file quartus produces specifies the timing delays in the FPGA. For example if I have a combinational block of logic in the design, does the .vho file always specify, the slowest possible time it could take for a signal to propagate through for a given speed grade? For example in my -4 (mid speed grade device), would the results of the timing simulation specify a delay on an FPGA which is almost a -5 i.e. a slow -4, or a typical -4 which is centered on the -4 distribution? Or is there a setting somewhere to specify this in Quartus? Likewise if a device is almost a -3, lets say there is one parameter that downbins it to a -4, would quartus produce the slowest possible timings in the .vho file? Also just one further question: Does the -3, -4 or -5 have any real meaning or is it just an arbitrary number assigned to specify the different speed grades. I read somewhere that for example -3 would mean a 3ns delay from point x to point y, but I´m not sure, perhaps it has a meaning to the design engineers regarding internals timings, but to the average user it´s just a number not required to be understood. Could somebody please clarify this. Thanks you very much for your time Ardni11 Replies
Altera_ForumThe timing delays are written to the accompanying .sdf files. (Standard Delay Format, I believe), and I think you'll get a slow model, which is based on your selected speed grade, and a fast model.
The slow model is the worst case analysis for every path in the design. The fastest is, well, the fastest. There is only one fast model, since FPGAs are not binned against this, and therefore any speed grade device could potentially be "fast". Note that these models are the same as the timing models used during static timing analysis. The numbers used to mean something with CPLDs, specifically they represented the Tpd for any two pins, so they would be marked -100, -70, -50 or newer stuff would be -15, 10 and -7. For the FPGAs they don't mean anything except relative to the others(smaller is faster.) Of course, there is no standard, as X flipped their numbering a while back, and for them the higher number is faster. Finally, just as an FYI, I see fewer and fewer people do timing simulations. Instead they do RTL simulations(much faster) and static timing analysis(more accurate from a timing perspective). That doesn't mean things won't be caught in a timing simulation, but the more synchronous design practices you follow, the less likely that is.
