Speed grades and internal timings

The timing delays are written to the accompanying .sdf files. (Standard Delay Format, I believe), and I think you'll get a slow model, which is based on your selected speed grade, and a fast model.

The slow model is the worst case analysis for every path in the design. The fastest is, well, the fastest. There is only one fast model, since FPGAs are not binned against this, and therefore any speed grade device could potentially be "fast". Note that these models are the same as the timing models used during static timing analysis.

The numbers used to mean something with CPLDs, specifically they represented the Tpd for any two pins, so they would be marked -100, -70, -50 or newer stuff would be -15, 10 and -7. For the FPGAs they don't mean anything except relative to the others(smaller is faster.) Of course, there is no standard, as X flipped their numbering a while back, and for them the higher number is faster.

Finally, just as an FYI, I see fewer and fewer people do timing simulations. Instead they do RTL simulations(much faster) and static timing analysis(more accurate from a timing perspective). That doesn't mean things won't be caught in a timing simulation, but the more synchronous design practices you follow, the less likely that is.