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Altera_Forum's avatar
Altera_Forum
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17 years ago

Speed grades and internal timings

Hi,

Not so much a problem that I´m having just more something I would like to understand better.

I am currently using a Stratix II GX I-Grade -4 FPGA for a project. I am using Modelsim to carry out timing simulations on my design and am wondering how the .vho file quartus produces specifies the timing delays in the FPGA.

For example if I have a combinational block of logic in the design, does the .vho file always specify, the slowest possible time it could take for a signal to propagate through for a given speed grade?

For example in my -4 (mid speed grade device), would the results of the timing simulation specify a delay on an FPGA which is almost a -5 i.e. a slow -4, or a typical -4 which is centered on the -4 distribution? Or is there a setting somewhere to specify this in Quartus?

Likewise if a device is almost a -3, lets say there is one parameter that downbins it to a -4, would quartus produce the slowest possible timings in the .vho file?

Also just one further question:

Does the -3, -4 or -5 have any real meaning or is it just an arbitrary number assigned to specify the different speed grades. I read somewhere that for example -3 would mean a 3ns delay from point x to point y, but I´m not sure, perhaps it has a meaning to the design engineers regarding internals timings, but to the average user it´s just a number not required to be understood. Could somebody please clarify this.

Thanks you very much for your time

Ardni

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Perhaps I have misinterpreted the meaning of 'gated clock' but would using using the altclkctrl megafunction be considered clock gating?

    I am using this megafunction in my current design to 'gate' a clock used to program a clock generater. The reason is to disable the clock once the generator is programmed after reset to save power. I saw in the timing simulation that the output of this buffer was skewed. I also recieved a warning in quratus saying :

    "found 1 node in clock paths which may be acting as ripple and / or gated clocks --nodes analyzed as buffer(s) resulting in clock skew. "

    Is it possible to use this megafunction and not recieve this warning? In my design, I am ignoring this warning (which I assume is safe to do) as it is only used to program the generator before being disabled.

    --- Quote End ---

    While clock control blocks for on-off gating are much preferred over doing the gating in logic resources, some of the issues discussed at http://www.alteraforum.com/forum/showthread.php?t=2388 will still apply. You can eliminate the Classic Timing Analyzer warning by assigning a derived-clock setting to the output of the clock control block, but that does not eliminate those considerations.