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Perhaps I have misinterpreted the meaning of 'gated clock' but would using using the altclkctrl megafunction be considered clock gating?
I am using this megafunction in my current design to 'gate' a clock used to program a clock generater. The reason is to disable the clock once the generator is programmed after reset to save power. I saw in the timing simulation that the output of this buffer was skewed. I also recieved a warning in quratus saying :
"found 1 node in clock paths which may be acting as ripple and / or gated clocks --nodes analyzed as buffer(s) resulting in clock skew. "
Is it possible to use this megafunction and not recieve this warning? In my design, I am ignoring this warning (which I assume is safe to do) as it is only used to program the generator before being disabled.
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While clock control blocks for on-off gating are much preferred over doing the gating in logic resources, some of the issues discussed at
http://www.alteraforum.com/forum/showthread.php?t=2388 will still apply. You can eliminate the Classic Timing Analyzer warning by assigning a derived-clock setting to the output of the clock control block, but that does not eliminate those considerations.
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