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Honored Contributor
Honored ContributorSource synchronous interface on Cyclone III without PLL
Hi, I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into ...
Altera_ForumHonored Contributor
Honored ContributorProgrammable in two regards: Either by a GENERIC parameter, that defines the number of logic elements in the delay chain or actually configurable at runtime by switching the signal route through multiplexers. I'm sure you can figure it out, if it's required for your design.
As often mentioned in the forum, logic cell delays aren't very exact, they depend on temperature and process variations. Routing delays are added to systematic logic cell delays and add uncertainty to the delay time calculation. You can assume a delay of about 0.2 to 0.25 ns per logic cell. Quartus simulator in timing simulation mode can give you a basic estimation of the results. How to implement logic cell delays in HDL code has been already discussed in the forum, it's also described in the Altera "Stratix Cookbook".
