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Contributor

5 years ago

Source synchronous interface design with Intel FPGAs for high speed ADCs

I need to design a source synchronous interface for high speed ADCs. I have not yet come across any Intel/Altera specific documentation on how to do this. If anything for this exists for Max 10 and C...

Ash_R_Altera

Regular Contributor

5 years ago

You can use the GPIO Lite Intel FPGA IP for DDIO. Please refer the documentation below:

https://www.intel.com/content/www/us/en/programmable/documentation/sam1393999966669.html#sam1394084519264

Regards.

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Source synchronous interface design with Intel FPGAs for high speed ADCs

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