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gyuunyuu's avatar
gyuunyuu
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4 years ago

Source synchronous interface design with Intel FPGAs for high speed ADCs

I need to design a source synchronous interface for high speed ADCs. I have not yet come across any Intel/Altera specific documentation on how to do this. If anything for this exists for Max 10 and C...
gyuunyuu's avatar
gyuunyuu
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4 years ago

The Max 10 IP catalogue does not contain many I/O functions as can be seen here:

For example, ALTDDIO_IN, ALTDDIO_OUT and ALTIOBUF are all missing. I take this to mean that Max 10 does not have capability to be interfaced with a 120 MHz ADC via DDR LVDS mode. Is this correct?