Forum Discussion

OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Source synchronous Input Constraints Edge Align

Hi following Altera/Intel course of about the source synchronous constraints https://learning.intel.com/Developer/learn/course/168/play/1632:223/constraining-source-synchronous-interfaces I ...
  • sstrell's avatar
    sstrell
    3 years ago

    You use the edge-aligned equations. The phase shift from the PLL happens inside the FPGA, not at the inputs, where the data and clock are still edge aligned. Use -setup and hold-period as shown.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

You use the edge-aligned equations. The phase shift from the PLL happens inside the FPGA, not at the inputs, where the data and clock are still edge aligned. Use -setup and hold-period as shown.