Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Source MAC address for TSE

I have synthesized TSE (Tripple Speed Ethernet) on DE2-115 Board, and I can see my frames on wireshark and on Logic Analyzer. But there is still one small problem, which is ...the source MAC address appears just 0s on both wireshark or logic analyzer. But on ModelSim source address looks as suppose to be (as I configured the registers). I have tried different senarios to show the source address within the frame, but none of them work. On my simulation the source MAC address is always correct as suppose to be. ....is there any idea why this is happenning?.

Rami

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    thank you socrates for your reply. I am not using any TCP/IP stack, I just instantiated the tripple speed ethernet megacore function. just the MAC layer.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    In this case, You have to set source MAC by Yourself. This is probably an option of the TSE itself, but TBH I am not sure, maybe You have to set PHY too?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    thank you again. absolutely true what you said about TSE and configuring source MAC address. I tried different senarios according to TSE documents, and they were fine in the simulation. But still the synthesis results show 0s on wireshark. I checked Marvell (PHY chip in DE2 board)document, and it does mention something about PHY_ADR[2:0] to configure..that's it, to configure, nothing is clear what is PHY_ADR[2:0], or what is even the pin map to it.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Those PHYAD pins are dedicated to select PHY address for MDIO connections. That has nothing to do with the MAC address. Check TSE again, You're probably configuring a wrong register or the values ar wrong.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for your reply. I see what are you saying.

    Again, my simulation results are Okay, nothing is wrong. source MAC and des. MAC are both OK in simulation, ...the des. MAC address is OK on wireshark as well. that means the synthesis is kinda correct.

    have you tried to synthesis TSE and connect DE2 board to an ethernet switch?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Thanks for your reply. I see what are you saying.

    Again, my simulation results are Okay, nothing is wrong. source MAC and des. MAC are both OK in simulation, ...the des. MAC address is OK on wireshark as well. that means the synthesis is kinda correct.

    have you tried to synthesis TSE and connect DE2 board to an ethernet switch?

    --- Quote End ---

    Thanks Rami_Amiri for posting this thread. I am interested in this issue also. If you can provide a link about the TSE material you are following?

    --- Quote Start ---

    Check TSE again, You're probably configuring a wrong register or the values ar wrong.

    --- Quote End ---

    Thanks Socrates for your explanation. I am trying to test in hardware a 10Gbps Ethernet subsystem (similar to TSE) in two Signal Integrity Stratix IV GT boards and having the same problem with accessing the register. Each component in the design has a memory space to store control, status or statistics with dedicated base address and several offsets. If you can tell me how the design author(s) allocate them and where they do this? if they assign them manually?

    I follow the design in this link:

    http://www.alterawiki.com/wiki/10g_ethernet_and_10g_base_r_phy_interoperability_hardware_demonstration_design

    Thank you very much.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I am following altera documents about TSE on their website. check this

    http://www.altera.com/literature/ug/ug_ethernet.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=tse

    or you can put "TSE" in altera's website.

    --- Quote End ---

    Thank you. Did you test in hardware with only one board for several loopback modes? Or you connect board to an Ethernet switch? I am curious about the second scenario, how can we realize that?

    How do you get the MAC addresses during the hardware test, by signalTap II or through system console tcl?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes, I have synthesized TSE on the FPGA , and then connected the DE2 board to a 1G ethernet switch. and a PC was connected with the switch.

    you need to map pin assignement with PHY chip. therefore instantiate the TSE and assigne the in/out pins.