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Altera_Forum
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14 years ago

Source MAC address for TSE

I have synthesized TSE (Tripple Speed Ethernet) on DE2-115 Board, and I can see my frames on wireshark and on Logic Analyzer. But there is still one small problem, which is ...the source MAC address ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Thanks for your reply. I see what are you saying.

Again, my simulation results are Okay, nothing is wrong. source MAC and des. MAC are both OK in simulation, ...the des. MAC address is OK on wireshark as well. that means the synthesis is kinda correct.

have you tried to synthesis TSE and connect DE2 board to an ethernet switch?

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Thanks Rami_Amiri for posting this thread. I am interested in this issue also. If you can provide a link about the TSE material you are following?

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Check TSE again, You're probably configuring a wrong register or the values ar wrong.

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Thanks Socrates for your explanation. I am trying to test in hardware a 10Gbps Ethernet subsystem (similar to TSE) in two Signal Integrity Stratix IV GT boards and having the same problem with accessing the register. Each component in the design has a memory space to store control, status or statistics with dedicated base address and several offsets. If you can tell me how the design author(s) allocate them and where they do this? if they assign them manually?

I follow the design in this link:

http://www.alterawiki.com/wiki/10g_ethernet_and_10g_base_r_phy_interoperability_hardware_demonstration_design

Thank you very much.