some warning i can't handle it ; whether these warnings existence is ok?

this code is used for the scan the 4 * 4 matrix keyboard

module keyboard(
        clk,rst_n,
        kbcol,
        kbrow,
        Bites
);
input clk,rst_n;
input  kbcol;
output  kbrow;
output  Bites;
//--------------------------------------------------
reg count;
always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)        count <= 0;
        else if ( count == 4 ) count <= 0;
        else count <= count + 1 ;
        end
        
reg  kbrow_r;
reg  sta;
        
always @ ( count ) begin
        case ( count )        
                2'b00 : begin        
                                        kbrow_r <= 4'b0001;
                                        sta <= 4'b00;
                end
                2'b01 : begin        
                                        kbrow_r <= 4'b0010;
                                        sta <= 4'b01;
                end
                2'b10 : begin        
                                        kbrow_r <= 4'b0100;
                                        sta <= 4'b10;
                end
                2'b11 : begin        
                                        kbrow_r <= 4'b1000;
                                        sta <= 4'b11;
                end
                default :;
        endcase
end
assign kbrow = kbrow_r;
reg  Bites_r;
always @ ( sta )        
        case ( sta )
                2'b00 : 
                        case (kbcol) 
                        4'b0001: Bites_r <= 8'h0f;
                        4'b0010: Bites_r <= 8'h0e;
                        4'b0100: Bites_r <= 8'h0d;
                        4'b1000: Bites_r <= 8'h0c;
                        default : ;
                        endcase
                2'b01 : 
                        case (kbcol) 
                        4'b0001: Bites_r <= 8'h03;
                        4'b0010: Bites_r <= 8'h06;
                        4'b0100: Bites_r <= 8'h09;
                        4'b1000: Bites_r <= 8'h0b;
                        default : ;
                        endcase                                                
                2'b10 : 
                        case (kbcol) 
                        4'b0001: Bites_r <= 8'h02;
                        4'b0010: Bites_r <= 8'h05;
                        4'b0100: Bites_r <= 8'h08;
                        4'b1000: Bites_r <= 8'h00;
                        default : ;
                        endcase        
                2'b11 : 
                        case (kbcol) 
                        4'b0001: Bites_r <= 8'h01;
                        4'b0010: Bites_r <= 8'h04;
                        4'b0100: Bites_r <= 8'h07;
                        4'b1000: Bites_r <= 8'h0a;
                        default : ;
                        endcase
                default : ;
        endcase
assign Bites = Bites_r;
endmodule

the main warning i was suspect is these

warning :

Warning (10235): Verilog HDL Always Construct warning at keyboard.v(57): variable "kbcol" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at keyboard.v(65): variable "kbcol" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at keyboard.v(73): variable "kbcol" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at keyboard.v(81): variable "kbcol" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10240): Verilog HDL Always Construct warning at keyboard.v(54): inferring latch(es) for variable "Bites_r", which holds its previous value in one or more paths through the always construct

Warning: Latch Bites_r[0] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[0]

Warning: Latch Bites_r[1] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[2]

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[2]

Warning: Latch Bites_r[2] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[1]

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[1]

Warning: Latch Bites_r[3] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[2]

Warning: Ports D and ENA on the latch are fed by the same signal kbcol[2]

Warning: Timing Analysis is analyzing one or more combinational loops as latches

Warning: Node "Bites_r[0]" is a latch

Warning: Node "Bites_r[1]" is a latch

Warning: Node "Bites_r[2]" is a latch

Warning: Node "Bites_r[3]" is a latch

Warning: Node "Bites_r[0]" is a latch

Warning: Node "Bites_r[1]" is a latch

Warning: Node "Bites_r[2]" is a latch

Warning: Node "Bites_r[3]" is a latch

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected gated clock "Mux8~0" as buffer

Info: Detected gated clock "Mux8~0" as buffer

please tell me the generate reason of these warning,and how to solve it ;thanks a lot ;