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Altera_Forum's avatar
Altera_Forum
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13 years ago

some problems of simulation with quartusII

I defined a output as out std_logic. But I didn't assign a value to it. If I use simulator tool to check the output. What will I get? is 'x' or '0'. I think it is 'x'. But I get the '0'. And ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you very much !

I used the Quartus internal simulator.

And I don't understand the second ----Which signal/net is actually driving the output?