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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

some problems of simulation with quartusII

I defined a output as out std_logic. But I didn't assign a value to it.

If I use simulator tool to check the output. What will I get? is 'x' or '0'.

I think it is 'x'. But I get the '0'. And sometime I get 'x' when I had a if statement.

Who can tell me the behavior of simulator in the quartusII?

Thank you very much

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The question isn't clear.

    - Which simulator are you referring to? Modelsim or Quartus (V9 and previous) internal simulator?

    - Which signal/net is actually driving the output?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you very much !

    I used the Quartus internal simulator.

    And I don't understand the second ----Which signal/net is actually driving the output?