Some help with code

Hi,
in principle, there's nothing against designing a pure combinational FPGA, e.g. a binary to seven-segment decoder as shown above.

By design, unregistered combinational logic has output glitches, but that's not necessarily a problem for a seven-segment decoder.
The worst point of the present design is the ineffective way to implement binary to BCD conversion. In an FPGA implementation, look-up table would be the best resource saving solution. Without block RAM, double dabble algorithm can reduce logic cell count.

Apart from ineffective implementation, I don't see a problem with code. It's producing correct output.

If it's intended as HDL learning project, I agree that synchronous design is preferred.