Soft LVDS aligned output clock

Hello Marco , About your second question.. Can you refer the Figure 2 in the below link , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf Block diagram clearly show how to connect the external i.e ATLPLL to the transmitter and receiver core clock . I dont think so you need a external clock out from transmitter, Receiver can generate there own reference clock and phase aligns with data stream. First question : Can you tell me in HW connection in your board are you having clock from transmitter to receiver ? Thank you , Regards, Sree