Honored Contributor
Honored ContributorHello foft et.al.,
Perhaps you (or anyone else) can help me, because I still do not understand the answer to your Problem 2 above. I too have SoCKIt, and am now on Mao VII tutorial (MD5 cracker). I just finished the Qsys design, which has an hps (with a conduit to on-chip memory) and three Avalon slaves which have avs_* signals connected to the AXI Master as well as md5_* signals exported as conduits to the verilog modules (which of course get implemented in the fpga portion). I did not do any manual pin assignments. Instead, the pin assignments were done by two processes, 1) the qsys generated TCL script for the memory pins, and 2) the fitter during compilation for all other pins/signals. My problem is this: the fitter produces some pin assignment that make no sense to me. For example, one of the conduit signals is a READDATA signal, and the fitter assigns it to pin AA16, which is a clock pin! How can that be? There are other examples which also do not make sense to me. Note AA16 is a clock pin both on the SOCKIT board schematic and on the Quartus Pin Planner instantiation of the Cyclone V 5CSXFC6D6F31C8 (which is the device on SOCKIT). I can understand the fitter does not know about SOCKIT, but it does (or should) know about the 5CSXFC6D6F31C8, AND SHOULD NOT ASSIGN A READDATA CONDUIT TO A CLOCK PIN. Can anyone please shed some light on this? There must be something basic I'm not understanding. THANKS! PS. I also don't understand why the READDATA conduit signal has to be assigned to a pin at all. It just comes from the fpga portion of the chip.
