Honored Contributor
Honored ContributorThanks BadOmen. Appreciated.
Quite a lot of my confusion before was that I was not understanding that the HPS configuration is separate form the FPGA configuration. So even though its designed as one unit in the FPGA there is another tool to then extract the HPS settings and create a pre-loader. Though I've still not tried this... Anyway the tutorials were all showing this by not, or partially, setting up the HPS side. In fact it seems the HPS side just needs instantiating in QSYS in order to allow the bridges to be used. It does not need configuring at all, except those parts that are related to the FPGA side (which bridges are active etc). I was further confused by the HPS crashing whenever I wrote to the FPGA via dd to /dev/fpga0. This turned out to be caused by a kernel module loaded by default in the GSRD. I removed gsrd_init.sh from /etc/init.d (Which runs mod probe gpio-altera) and then it all behaves much better. I can flash the FPGA side without the kernel crashing! Also the bridges pretty much 'just work', once I get my avalon mm signals right. It turns out the altera fabric deals with all the clock domain crossing issues and I can just clock the FPGA side of the avalon MM interface as I wish. Which makes things much easier than I was worrying. My remaining challenges are to get USB working and DDR3 SDRAM FPGA side working. I bought a USB OTG->USB adaptor but the kernel does not recognise any devices. I see no usb host modules in /lib/modules so I guess I need to build my own kernel in order to get that going. Did anyone manage to get USB OSG host working with the GSRD? As for DDR3 SDRAM, it looks really complex! I'm familiar with 'old' SDRAM having written my own basic controllers, calculated PLL phase offsets etc. The DDR3 looks a bit 'next level' though that is simplified by the Altera IP. So I tried adding the UNIPHY in QSys but the connections make no sense to me. I was hoping there was a way to present the SDRAM as something like an avalon MM slave that I can run my own clock line to. Anyway sure I'll figure it out... I hope! --- Quote Start --- I'm not really following problem# 1 so here is some info that might connect the dots. Qsys generates RTL to a subdirectory named after whatever you called the system. In that RTL that was generated should be a verilog file that represents the Qsys system and all the interfaces exported out of the system so you would just instantiate that module Qsys top level module in your VHDL RTL. Quartus will know where all those Qsys generated files are because you included the .qip file which references all that stuff. --- Quote End --- I'm including the .qip file. It just seems I need to add a component section to my architecture in order to use it. This seemed odd to me. However in qsys there is a menu setting to generate a 'vhdl usage example' from which I can cut and paste the component. I found this video quite helpful, though its for a different board: https://www.youtube.com/watch?v=2wuket4-q7q --- Quote Start --- Problem# 2. You'll need to run a .tcl script that was generated by the SDRAM portion of the HPS. You have to do the same thing when instantiating the SDRAM controller in non-SoC devices too so this is documented in the memory controller documentation. Off the top of my head it'll be called something like <HPS/SDRAM instance name>pin_assignments.tcl and is generated in that subdirectory that Qsys generated the RTL into. Problem# 3 The HPS pins are fixed so you don't need to assign them like you typically do with FPGA I/O but they'll still need to be connected to ports in the top level. When the HPS boots information about the HPS pins are used by the preloader to configure them. The FPGA and it's I/O are configured when the FPGA side of the device is configured either by an external programmer or by the HPS under software control. Interfaces such as the bridges would be connected to other IP in the Qsys system and not connected to ports in the top level. --- Quote End --- Thanks. I see now these are external HPS pins. which programming the FPGA does not configure. If I just run the .tcl script (I was doing that) then the fitter complains about no pin locations. So I assigned explicit locations to the HPS pins as shown in the video above. I think these are not used except by the preloader, I'm not sure if there is any harm in not connecting them if not using that. Thanks for all the help and advice. Still lots to learn about this board but its getting clearer! My core is now running pretty well. If I can get USB and SDRAM going I'll be happy:-)
