Honored Contributor
Honored ContributorI'm not really following problem# 1 so here is some info that might connect the dots. Qsys generates RTL to a subdirectory named after whatever you called the system. In that RTL that was generated should be a verilog file that represents the Qsys system and all the interfaces exported out of the system so you would just instantiate that module Qsys top level module in your VHDL RTL. Quartus will know where all those Qsys generated files are because you included the .qip file which references all that stuff.
Problem# 2. You'll need to run a .tcl script that was generated by the SDRAM portion of the HPS. You have to do the same thing when instantiating the SDRAM controller in non-SoC devices too so this is documented in the memory controller documentation. Off the top of my head it'll be called something like <HPS/SDRAM instance name>pin_assignments.tcl and is generated in that subdirectory that Qsys generated the RTL into. Problem# 3 The HPS pins are fixed so you don't need to assign them like you typically do with FPGA I/O but they'll still need to be connected to ports in the top level. When the HPS boots information about the HPS pins are used by the preloader to configure them. The FPGA and it's I/O are configured when the FPGA side of the device is configured either by an external programmer or by the HPS under software control. Interfaces such as the bridges would be connected to other IP in the Qsys system and not connected to ports in the top level. Problem# 4 By default when you create a new system Qsys assumes you'll be needing a clock source from outside the Qsys system which is almost always the case. This isn't anything to do with the SoC that's just the behavior of the tool. You can use that clock input or use a clock generated from the HPS which is why you almost always need an external clock source since the clock has to come from somewhere (and if you instantiate a Qsys PLL it still needs an input from outside the system). I typically don't use the HPS clocks so that I can work on the FPGA side of the design without having to worry about the HPS being booted to the point where that clock is functional. You need a clock to be connected to all IP in Qsys because the Avalon and AXI connections need to be clocked by something. The synchronous interfaces like the bridges and the FPGA-to-SDRAM ports need to be connected to a clock in the Qsys system since the HPS PLLs only clock the logic on the hard silicon side so the FPGA facing side needs a clock too. If you haven't already done so I *highly* recommend taking a look at the design that ships with that kit because it'll give you a better idea how the HPS gets integrated into the FPGA design. Also if you are new to Qsys it's probably worth becoming familiar with a tutorial or online course for it so that you'll know what all it's doing behind the scenes for you and why it's being used.
