Single wire can bus and bidirectional pin coding

CAN is designed to detect bus contention by the dominant/recessive level concept.

I'm not sure how your actual hardware is related to single wire CAN specification, obviously a FPGA pin never meet the specification. I understand you are implementing a similar function on a board level. But it would use somehow the dominant/recessive signalling concept, e.g. an open drain 'H' driver together with a pulldown resistor.

In this case, you can readback the pin level while driving out. Contention will be detected if you drive recessive state '0' but read '1'.