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I think, the question can't be answered without an exact specification of intended behaviour.
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The register that I am concerned about:
A simple system connection:
MCU <====SPI====> FPGA <==1-wire CAN=> SLAVE device(s)
1. The FPGA detects one or more slave devices (i.e. max of 8).
2. FPGA updates its register for each of the 8 devices. (i.e. 1' for connected, '0', for disconnected)
3. FPGA sends an interrupt to notify the MCU about new devices
4. MCU uses SPI to read the registers FPGA, and writes back to the same register with respective '0's once it has processed the newly connected device(s).
The point to note is that it might be possible for devices to be connected at any time. Meaning there is a chance there is write contention on the register.
Unfortunately I am unable to change the process on how the device registration takes place, as this is specified in the specifications.
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Obviously it's impossible for a bidirectional output with tristate driver.
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Thanks, I thought it might sound stupid but I'd ask anyway.
Honored Contributor
