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I have another question, unrelated to bidirectional ports.
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I think, the question can't be answered without an exact specification of intended behaviour.
Particularly:
- intended reaction on conflicting writes
- presumed SPI bus and user logic are unrelated clock domains, you might read inconsistent data when a register is updated at the same time. What's the expected behaviour in this regard?
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Is it possible receive data from the slave without driving the bidirectional port with 'Z' on the master side?
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Obviously it's impossible for a bidirectional output with tristate driver.
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This is the RTL representation of the bidir port in Quartus:
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The tristate driver in front of a register is useless (and won't be synthesized). Tristate driver can be only implemented on external pins, internal tristate drivers are converted to multiplexers (if meaningful at all).
I'm not familiar with "single wire" can, but I guess it should use majority logic as standard can bus. Using FPGA, an open drain driver with pull-up would be the nearest equivalent.
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