Single wire can bus and bidirectional pin coding

The first thing is that you need to model the open-drain and the pull-up separately.

You should have a testbench which models the pull up by always driving the signal with a weak high, while also connecting it to slaves.

bidir_bus_signal <= 'H';
slave1 : my_slave 
port map (
	...
	bidir_port => bidir_signal,
	...
);

Then, inside your slave_controller, you implement the open drain by driving the port with either '0' or 'Z'.

bidir_port_i <= to_x01(bidir_port);
bidir_port <= '0' when bidir_port_oe = '1' and bidir_port_o = '0' else 'Z';

Your slave logic should drive the bidir_port_oe and bidir_port_o signals to drive the output and it should read from bidir_port_i to read the input.

A couple of implementation details:

- Quartus knows the code template above and it will set the I/O driver to open-drain.

- In FPGAs, do not use tri-state logic outside the top level module. Instead, if you need to connect your bidir_port to modules inside your toplevel, use the trio of bidir_port_i, bidir_port_oe and bidir_port_o.