Singed M_by_M multiplication

Are you asking about how this type of multiplier works at silicon level (its architecture) or are you asking how to multiply in fpga?

I personally don't know about various architectures of multiplier technology, I just multiply and get the output and leave that to the tool.

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Are you asking about how this type of multiplier works at silicon level (its architecture) or are you asking how to multiply in fpga?

I personally don't know about various architectures of multiplier technology, I just multiply and get the output and leave that to the tool.

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thanks for replying Kaz, i meant the architecture, i want to implement my own, i did the unsigned on but not familiar with the signed one(s)...

We here work on fpga platforms and make use of ready-made blocks of rams/mults/possibly adders/PLL/serdes ..etc. The rest of functions are left to designers to implement in the logic fabric. So we have little choice of available sub-components.

I know Universities don't draw a clear line between fpga and asic as they prepare students for all areas. Thus the best place for your question is an ASIC forum, they are proud people and know a lot about silicon level design.

Some examples of multiplier architectures are discussed in the Quartus Advanced Synthesis Cookbook

http://www.altera.com/literature/manual/stx_cookbook.pdf

Personally, I'm satisfied with the multiplier implementation of the Quartus integrated synthesis, particularly using FPGA hardware multipliers of recent FPGA families.