Forum Discussion
Honored ContributorSimulink IIR Bandpass filter on DE2
I made a filter with matlab simulink and used one of its tools to create vhdl code out of it. I implemented it on an FPGA and it gives me reasonable output except that the frequencies that it pass are not the frequency I designed it to pass. When testing in matlab, a FFT of the output from the filter gives a single peak at 82Hz, but the filter on the board passes 56Hz as well at 170Hz. Any idea what would cause this? Thanks for the help.
6 Replies
Altera_ForumAlright, I'm sorry to dissapear and reappear with such a change in problem but...
I realized part of my problem is that I'm not converting the bitstream out of the codec into parallel quite correctly. Also, I can't quite seem to turn off bypass mode. In fact, I compiled and ran a project provided by altera and it lists that it's not in bypass mode, but it seems to still be bypassing. Does anyone have any insight on this? I am including the project zipped up as an attachment.- Altera_Forum
I wonder, which filter specification is represented by the VHDL code. The coefficients look strange.
- Altera_Forum
Would my vhdl code be at all useful? It was created automatically by Matlab Simulink. I attached the .vhd file. I hope that works.
- Altera_Forum
ADCLRC seems reasoanable as a filter sampling clock. The results seem to indicate, that the actual clock frequency is different from calculated value.
The said 170 Hz looks like a 3rd harmonic, either caused by a distorted signal source, ADC overload or filter truncation errors (You didn't tell about relative amplitudes or the filter word length). - Altera_Forum
I'm sorry to have been vague. I am implementing this filter on a Cyclone II DE2. I'm feeding data in from the audio codec. I'm using the ADCLRC clock. Would that be correct or incorrect?
- Altera_Forum
The question doesn't seem particularly related to Altera FPGA or tools, but did you set the correct clock frequency when creating the filter?
