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Oh yes, I do do that. But no matter how much ever I change the the clock signal to high or low, I get the same result. In some case, it takes the previous output result and then never change despite changing the inputs.
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Hi,
I assume your are using the standard setting of the simulator. This means your are running a simulation where the timing of your FPGA is taken into account. You have
also the choice to use a "functional" simulation which don't use the timing. With this
simulation you can check whether your design is "logical" correct working or not. You can
change the setting in the simualtor itself. There is a field "simulation mode", change the
setting to "functional" and generate a netlist ( press the button nearby) and re-run your simulation.
Kind regards
GPK
Honored Contributor
