Simulation

Always block doesn't have sensitivity list, you should write something like

always @*
begin
<...>
end

The main problem with your code though is that you try to change clock signal by itself (I don't know how to better put it).

Anyway, try this:

`timescale 1ns / 1ps
module tb_clk_gen ();
reg SYS_RST;
reg SYS_CLK;
initial
begin:Reset_Gen
SYS_RST <= 1'b0;# 50 SYS_RST <= 1'b1;
end
initial
begin:Clock_Gen
SYS_CLK <= 1'b0;
wait (~SYS_RST);
forever# 10 SYS_CLK <= ~SYS_CLK;
end
endmodule

Hi, AndrewS6:

Thanks. But there's another bug~

code 1:

--- Quote Start ---

initial begin

SYS_CLK <= 0;

$display($time, "SYS_CLK = 0");

forever# (SYS_CLK_PERIOD/2) SYS_CLK <= ~ SYS_CLK;

$display($time, "SYS_CLK reverse");

CD_PULSE <= 0;

$display($time, "CD_PULSE = 0");

forever# (CD_PULSE_PERIOD/2) CD_PULSE <= ~ CD_PULSE;

$display($time, "CD_PULSE reverse");

end

--- Quote End ---

http://www.alteraforum.com/forum/attachment.php?attachmentid=3821&stc=1&d=1300376027

code 2:

--- Quote Start ---

initial begin

SYS_CLK <= 0;

$display($time, "SYS_CLK = 0");

forever# (SYS_CLK_PERIOD/2) SYS_CLK <= ~ SYS_CLK;

$display($time, "SYS_CLK reverse");

end

initial begin

CD_PULSE <= 0;

$display($time, "CD_PULSE = 0");

forever# (CD_PULSE_PERIOD/2) CD_PULSE <= ~ CD_PULSE;

$display($time, "CD_PULSE reverse");

end

--- Quote End ---

http://www.alteraforum.com/forum/attachment.php?attachmentid=3822&stc=1&d=1300376034

I just put the CD_PULSE and SYS_CLK assignment in different initial block and the result is right. I am still confused about that. Hope you can help me with this.

Hello.

In your first example Modelsim executes only first forever line, other lines are not executed (you can verify this by placing breakpoint at second forever operator). This is correct operation as forever operator should be used only once in each initial block. Your second code example demonstrates just that.

I suggest you to read more about behavioral modeling so you can use this very powerful tool more precisely. See link for example:

http://www.asic-world.com/verilog/vbehave1.html