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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Simulation

My testbench couldn't generate clock wave. The code is : //-------------------------- always //@ (SYS_RST, SYS_CLK) // optional sensitivity list // @(event1 or event2 or .... eventn) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Always block doesn't have sensitivity list, you should write something like 


always @*
begin
<...>
end
The main problem with your code though is that you try to change clock signal by itself (I don't know how to better put it).

Anyway, try this: 


`timescale 1ns / 1ps
module tb_clk_gen ();
reg SYS_RST;
reg SYS_CLK;
initial
begin:Reset_Gen
SYS_RST <= 1'b0;# 50 SYS_RST <= 1'b1;
end
initial
begin:Clock_Gen
SYS_CLK <= 1'b0;
wait (~SYS_RST);
forever# 10 SYS_CLK <= ~SYS_CLK;
end
endmodule