Forum Discussion
Altera_Forum
Honored Contributor
15 years agoSimulation
My testbench couldn't generate clock wave. The code is : //-------------------------- always //@ (SYS_RST, SYS_CLK) // optional sensitivity list // @(event1 or event2 or .... eventn) ...
Altera_Forum
Honored Contributor
15 years agoHello.
In your first example Modelsim executes only first forever line, other lines are not executed (you can verify this by placing breakpoint at second forever operator). This is correct operation as forever operator should be used only once in each initial block. Your second code example demonstrates just that. I suggest you to read more about behavioral modeling so you can use this very powerful tool more precisely. See link for example: http://www.asic-world.com/verilog/vbehave1.html